CPLD (Complex programmable logic device)

Altera Max V CPLD

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Leveraging the successful MAX® II architecture, MAX® V devices combine instant-on, non-volatile CPLD characteristics with advanced features typically found in FPGAs, such as phase-locked loops (PLLs), on-chip memory, and internal oscillators.

The MAX V CPLD includes an array of logic elements (LEs grouped in logic array blocks (LABs)), memory resources (non-volatile flash and LE RAM), digital PLLs, global signals (clocks or control signals), and a generous amount of user I/Os. The MultiTrack interconnect is designed to maximize performance and minimize power by using the most efficient, direct connection from input to logic to output.

  • Up to 50% lower total power compared to equivalent density competitive CPLDs, generating less heat and saving battery power.
  • Replaces an external discrete timing devices for use as a simple clocking source, saving BOM costs.
  • Power on and reset quickly (500 µs or less), ideal for power management, power sequencing, and monitoring of other devices on the PCB.
  • Allow you to update a second configuration image while the CPLD is in operation.
  • I/Os are hot-socket compliant and support LVTTL, LVCMOS, PCITM, and LVDS output interface standards, along with other bus-friendly options (e.g. output enable per pin, Schmitt triggers, slew rate control, and others).
  • The on-chip JTAG block can configure external non-JTAG-compliant devices, such as discrete flash memory devices, using the Parallel Flash Loader IP Megafunction.

Architecture

The MAX® V CPLD architecture supports MultiVolt I/O functionality, allowing different I/O banks to operate with different I/O voltages to seamlessly connect to other devices. The device core is powered by a single 1.8-V external supply (VCCINT), providing CPLD functionality with low dynamic and stand-by power.

Datasheet

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